Job Description
KEY RESPONSIBILITIES:
* Collaborate with architects and design engineers to understand the current features to be verified

* Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases

* Estimate the time required to write the new feature tests and any required changes to the test environment

* Build the directed and random verification tests

* Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues

* Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements

PREFERRED EXPERIENCE:
* Prior experience in ASIC verification




* Extensive experience in designing and implementing self-checking testbenches, coverage closure techniques and regression management flows
* In depth knowledge of modern verification practices including UVM, Formal Verification and assertion-based test
* Experience and knowledge of communications standards (such as Ethernet, Flex Ethernet, OTN, Interlaken)
* Fluency in Verilog or System Verilog
* Excellent written and verbal communication skills

ACADEMIC CREDENTIAL:
Bachelor in Electrical/Computer/Software Engineering, Master degree an asset

Must Have:
Write and debug UVM Test
10 + Years experience needed

📌 Verification Lead (Hyderabad)
🏢 Mirafra Technologies
📍 Hyderabad