Role Description
Who we are:
At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact—touching billions of lives in the process. Visit us at .
Summary
UST is looking for a SoC Design Verification Engineer with expertise in SystemVerilog, UVM, and functional verification of complex SoC/IP designs.
The Opportunity
We are seeking a motivated SoC Design Verification Engineer to verify complex digital IPs and SoCs across various stages of the development cycle. The ideal candidate will work closely with design, architecture, and validation teams to ensure first-pass silicon success through robust verification methodologies.
Key Responsibilities
• Develop and execute verification plans for IP and SoC-level features
• Create and enhance UVM/SystemVerilog-based verification environments
• Develop testcases, sequences, checkers, assertions, and coverage models
• Perform functional, regression, and system-level verification
• Analyze simulation results and debug RTL/design issues
• Drive coverage closure including code, functional, and assertion coverage
• Collaborate with RTL designers to resolve verification and integration issues
• Participate in design reviews and verification sign-offs
• Support SoC integration, subsystem verification, and silicon bring-up activities
Required Qualifications
• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or related field
• 2-5 years of experience in SoC/IP Design Verification
• Strong knowledge of SystemVerilog and UVM methodology
• Positive understanding of digital design fundamentals, RTL, and computer architecture concepts
• Experience in developing verification environments, testbenches, and regression suites
• Strong debugging skills using simulators such as VCS, Xcelium, or Que
📌 Associate II (Bengaluru)
🏢 UST
📍 Bengaluru