Job Title: SOC Verification Engineer
Location: Bengaluru (Onsite)
Experience: 2 to 5 Years
Job Summary:
We are seeking a highly motivated SoC Design Verification Engineer with 2 to 5 years of experience in ASIC/SoC verification. The candidate will be responsible for developing and executing verification strategies for complex SoC designs, ensuring functional correctness and quality throughout the product development lifecycle.
Key Responsibilities:
• Develop and implement verification plans based on design specifications and architecture requirements.
• Create and maintain SystemVerilog/UVM-based verification environments for IP, subsystem, and SoC-level verification.
• Develop test cases, sequences, scoreboards, checkers, assertions, and coverage models.
• Perform functional verification using simulation, regression, and coverage analysis methodologies.
• Debug RTL and verification setting issues, working closely with design and architecture teams.
• Analyze functional, code, assertion, and toggle coverage metrics and drive closure.
• Support integration and verification of industry-standard protocols such as AXI, AHB, APB, PCIe, USB, Ethernet, UART, SPI, or I2C.
• Participate in design reviews and verification sign-off activities.
• Automate verification flows using scripting languages.
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Required Qualifications:
• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
• 2 to 5 years of experience in ASIC/SoC Design Verification.
• Solid understanding of digital design fundamentals and computer architecture.
• Hands-on experience with SystemVerilog and UVM methodology.
• Experience in writing verification test plans, test cases, assertions, and coverage models.
• Good debugging skills using simulators such as VCS, Xcelium, QuestaSim, or Riviera.
• Knowledge of industry-standard bus protocols such as AXI, AHB, APB, and peripheral interfaces.
• Understanding of coverage-driven verification and constrain
📌 SOC Verification Engineer (Bengaluru)
🏢 UST
📍 Bengaluru