Memory Layout / Custom Layout .
Hands-on experience with
Cadence Virtuoso .
Positive understanding of
DRC/LVS/ERC
and physical verification.
Experience with
Calibre
or equivalent verification tools.
Good understanding of CMOS devices, matching techniques, common-centroid layout, shielding, guard rings, and routing.
Experience with
advanced technology nodes
is an added advantage.
Ability to interpret schematics and work independently on layout implementation.SRAM / ROM / Register File / Memory Compiler layout.
Advanced-node memory layout experience.
Experience with
TSMC / Samsung / GlobalFoundries
technologies.
Experience working on full-custom analog/mixed-signal environments.