Responsibilities

- block level / top-level floor planning
- PG Planning
- partitioning (for hierarchical designs)
- placement
- scan-chain-reordering
- clock tree synthesis
- timing optimization
- SI aware routing
- timing analysis/closure and ECO tasks (timing and functional ECOs)
- SI closure
- design rule checks (DRC)
- Logical vs. Schematic (LVS) checks

- Antenna checks
- be able to fix the violations
- Provide technical guidance, mentoring to physical design engineers
- Interface with front-end ASIC teams to resolve issues

- Excellent communication skills
- Robust background of ASIC Physical Design: Floor planning, PR, extraction, IR Drop Analysis, Timing and Signal Integrity closure
- Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools

- Expertise in scripting languages such as PERL, TCL
- Strong Physical Verification skill set
- Static Timing Analysis in PrimeTime or PrimeTime-SI
- Good written and oral communication skills.

Ability to clearly document plans

- Ability to interface with different teams and prioritize work based on project needs

Requirements
- Experience 3 to 8 Years
- Location: Hyderabad

📌 Senior Engineer - Physical Design (Hyderabad)
🏢 MosChip®
📍 Hyderabad