Job Summary

We are seeking a hands-on RTL Design Lead with strong micro-architecture and RTL development experience to design and deliver high-quality, production-ready RTL for AI/ML accelerators, Network-on-Chip (NoC) fabrics, and low-power SoCs. The role spans the complete design lifecycle from architectural definition to silicon tape-out, with opportunities to lead small design teams and influence system-level decisions.

Responsibilities

- Own micro-architecture definition and RTL design of complex IP blocks and subsystems.

- Develop clean, modular, and synthesizable SystemVerilog RTL aligned with ASIC sign-off requirements.

- Design and implement high-performance pipelines, FSMs, arbiters, datapaths, and control logic.

- Apply low-power design techniques including clock gating, power gating awareness, multi-Vt strategies, and UPF-aware RTL design.

- Lead and technically mentor a small team of RTL engineers; perform detailed design reviews.

- Work closely with architecture, verification, physical design, and DFT teams to ensure correct and productive implementation.

- Support synthesis, timing closure, power analysis, and ECO cycles through tape-out.

- Debug functional, CDC, and reset-related issues across block and subsystem boundaries.

- Ensure design quality through coding guidelines, lint, CDC/RDC, and design checklists.

- Contribute to design documentation and micro-architecture specifications.

Requirements

- 5-8 years of hands-on RTL design experience in ASIC or advanced FPGA environments.





- Strong proficiency in SystemVerilog for RTL design (FSMs, pipelines, arbiters, datapaths).

- Solid understanding of clocking strategies, resets, CDC/RDC, and timing concepts.

- Experience working with standard ASIC design flows (lint, synthesis, STA, ECO).

- Ability to own blocks end-to-end and deliver sign-off-quality RTL.

- Strong debugging, problem-solving, and communication skills.

Preferred Qualifications

- Experience designing AI/ML accelerators, DSP blocks, or NoC/interconnect fabrics.

- Exposure to UPF-based low-power design and multi-power-domain SoCs.

- Prior FPGA prototyping or silicon tape-out experience.

- Familiarity with performance, power, and area trade-offs at the micro-architecture level.

- Experience collaborating in multi-site or cross-functional engineering teams.

Benefits

- Opportunity to work on cutting-edge AI/ML and low-power SoC designs.

- Ownership of critical IP blocks with real impact on silicon.

- Exposure to full chip lifecycle from architecture to tape-out.

- Collaborative environment with experienced architects, verification, and PD teams.

Qualifications

- B.Tech / B.E. in Electronics, Electrical Engineering, or Computer Science.

- M.Tech / MS is a plus.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 RTL Design Lead (Kochi)
🏢 Tosil System
📍 Kochi