Location: Noida/Bengaluru/Hyderabad /n Experience: 8+ Years /n Employment Type: Full-time /n Job Overview /n We are looking for an experienced Memory Circuit Design Engineer to join our semiconductor design team and work on the design and development of advanced memory circuits and memory macros. /n The ideal candidate will have strong hands-on experience in transistor-level memory circuit design, memory architecture, circuit optimization, SPICE simulation, and PVT/corner analysis. The role will involve working closely with architecture, layout, characterization, verification and physical design teams to deliver robust, high-performance and low-power memory solutions. /n Key Responsibilities /n /n

- Design and develop memory circuits and memory macros at transistor level.

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- Work on memory architectures such as SRAM, Register File, ROM and/or DRAM, depending on project requirements.

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- Develop and optimize critical memory circuits including:

/n /n Memory bitcells /n Sense amplifiers /n Write drivers /n Precharge/equalization circuits /n Row/column decoders /n Wordline drivers /n Column muxing /n Address buffers /n Read/write control circuits /n Assist circuits /n Timing/control circuits /n /n

- Perform schematic design and transistor-level simulations using SPICE-based simulators.

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- Analyze memory performance across PVT corners, voltage ranges and temperature conditions.

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- Optimize memory designs for:

/n /n Read/write performance /n Access time /n Leakage power /n Dynamic power /n Area /n Stability /n Yield and robustness /n /n

- Perform Monte Carlo and statistical analysis to evaluate process variation and mismatch.

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- Analyze memory failure mechanisms including read stability, write ability, leakage, disturb conditions and sense-margin issues.

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- Develop and optimize memory circuits for low-voltage and low-power operation.

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- Work with layout engineers to ensure robust implementation and minimize layout-dependent effects.

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- Review and analyze post-layout simulations, including extracted parasitics.

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- Support characterization of memory macros across different PVT conditions.

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- Debug circuit-level issues and identify root causes of performance, functionality or yield degradation.

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- Collaborate with architecture, layout, verification, characterization and technology teams throughout the design cycle.

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- Contribute to design reviews, technical documentation and design methodology improvements.

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- Support silicon bring-up, silicon correlation and post-silicon debug, wherever applicable.

/n /n Required Skills & Experience /n /n

- 8+ years of hands-on experience in Memory Circuit Design / Memory IC Design.

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- Strong experience in transistor-level circuit design.

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- Strong understanding of CMOS circuit design and semiconductor device fundamentals.

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- Hands-on experience with one or more memory technologies:

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- SRAM

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- DRAM

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- Register File

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- ROM

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- Robust understanding of memory architecture and critical memory circuits.

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- Experience designing and optimizing bitcells and peripheral circuits.

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- Strong hands-on experience with SPICE simulations and circuit-level debugging.

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- Experience with Cadence Virtuoso and Spectre or equivalent tools.

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- Strong experience with:

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- PVT analysis

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- Monte Carlo analysis

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- Corner analysis

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- Post-layout simulation

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- Parasitic analysis

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- Understanding of memory timing and performance parameters.

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- Experience with circuit optimization for power, performance, area and robustness.

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- Strong understanding of process variation, mismatch and reliability considerations.

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- Ability to work independently on circuit design problems and drive them to closure.

/n /n Preferred / Good-to-Have Skills /n /n

- Experience with advanced CMOS/FinFET technology nodes.

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- Experience with high-density SRAM or embedded memory macros.

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- Experience with high-speed memory design.

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- Experience with low-voltage SRAM design.

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- Knowledge of:

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- SRAM stability

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- SNM

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- Write Margin

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- Read Margin

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- Assist techniques

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- Leakage reduction

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- Variation-aware design

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- Sense amplifier offset

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- Bitline architecture

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- Experience with DRAM peripheral circuit design, if applicable.

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- Exposure to memory compiler / memory macro development.

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- Experience with memory characterization and Liberty/model generation.

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- Familiarity with Calibre DRC/LVS/PEX and post-layout verification.

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- Experience working with advanced-node design challenges.

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- Scripting knowledge in Python, Perl, Tcl or SKILL is a plus.

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- Experience with silicon correlation and post-silicon debug is highly desirable.

/n /n Tools /n Primary: /n /n

- Cadence Virtuoso

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- Spectre / Spectre X / FastSPICE

/n /n Physical Verification / Extraction: /n /n

- Calibre

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- PEX / RC extraction tools

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- SPICE

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- Monte Carlo

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- PVT / Corner Analysis

/n /n Scripting: /n /n

- Python

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- Tcl

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- Perl

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- SKILL

/n /n Education /n /n

- B.E./B.Tech/M.E./M.Tech in Electronics & Communication, Electrical Engineering, VLSI or related disciplines.

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📌 Memory Circuit Design Lead (Noida)
🏢 leadIC Design
📍 Noida