- The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.
- Should have experience in atleast one : MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys.
- Positive to have worked on zero delay as well as SDF Timing Simulations.
- Should have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
- Good to have worked on fault models like stuck-at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques.
- Candidate should have worked in SoC level DFT with experience in OCC/OPCG insertion,
EDT/Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and /or production activities with exposure to Tester debug usings shmoo plots and graphs.
- The candidate should have experience of providing test mode timing constraints to STA and PD teams.
Preferred candidate profile
Candidate should have experience in any of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.
Should be okay for working from office but it could be hybrid or remote depending on projects