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MTS Silicon Design Engineer – Constraints & Full-Chip Timing (FCT)
Role Summary
Responsible for developing, validating, and maintaining timing constraints and driving full-chip timing convergence for complex SoCs. The engineer will own SDC methodology, timing signoff quality, cross-domain timing closure, and collaborate with RTL, Architecture, Tile PnR, Clocking, DFT, and Full-Chip teams to achieve timing signoff targets across all project milestones.
Key Responsibilities
• Develop, validate, and maintain block, subsystem,



and SoC-level timing constraints (SDC).
• Perform comprehensive timing analysis and closure for full-chip and partition-level designs.
• Analyze setup, hold, SI, OCV, AOCV, POCV, CDC-related, and mode-specific timing violations.
• Drive timing convergence across multiple corners, modes, and milestone releases.
• Debug timing issues originating from RTL, constraints, clock architecture, physical implementation, and ECO changes.
• Own timing signoff readiness and ensure timing quality across all project deliverables.
• Collaborate with Tile PnR, Clocking, DFT, Integration, and RTL teams to resolve critical timing bottlenecks.
• Develop timing automation, QoR dashboards, and methodology improvements to improve closure efficiency.
• Support customer timing reviews, signoff audits, and tapeout readiness activities.
• Mentor junior engineers and provide technical guidance on timing methodologies and best practices.

📌 FCT PD lead (Bengaluru)
🏢 Advanced Micro Devices
📍 Bengaluru