Navii is an AI recruiter, running this search on behalf of Proxelera.
HERE'S HOW IT WORKS
Rather than your resume sitting in a queue, you have a conversation with Navii about your experience and what you want next. What you say reaches Proxelera's hiring team in your own words. It is a required step, and there is nothing to schedule.
NEXT STEP
A conversation with Navii about this role:
https://app.heynavii.ai/careers/verification-engineer-7e701210
ABOUT PROXELERA
Proxelera builds chip, systems, and software solutions for global leaders—and right now we need two strong verification engineers to keep engineering output moving without slip-ups. If you’ve spent years turning complex specs into coverage-driven, assertion-rich verification that actually finds bugs (and helps teams ship faster), this is your seat.
The Work
• Own functional verification for complex ASIC/System-on-Chip designs, end-to-end from early verification planning through tape-out readiness.
• Build and maintain functional verification environments using SystemVerilog + UVM.
• Drive coverage-driven verification using functional coverage, SVA assertions, and coverage closure strategies.
• Debug hard failures by triaging root cause across stimulus, DUT behavior, and environment issues.
• Use industry-standard simulators such as Questa or VCS to reproduce issues, validate fixes, and ensure verification completeness.
What You’ll Need (Must-Haves)
• 6+ years of hands-on experience in functional verification.
• Strong SystemVerilog and UVM expertise.
• Experience with functional coverage, assertions (SVA), and coverage-driven verification.
• Solid debugging and problem-solving skills in verification projects.
• Experience with Questa or VCS.
• Evidence of complete full-chip design-cycle experience—from design concept/early verification planning through tape-out handling of complex verification assignments.
• Full-chip experience must reflect ownership beyond IP/block-level verification (IP/block-only