About Company

Tsavorite Scalable Intelligence is building a new foundation for AI computing. We design silicon, systems, and software that work as one, bringing together general-purpose processing, AI acceleration, and scalable memory in a single architecture. From edge devices to data centers, our goal is to make advanced AI more powerful, efficient, and accessible.

Our founding team has a track record of shipping the highest performance silicon and we have engineering teams in the US and India. We are looking for curious, driven people across disciplines who want to turn ambitious engineering into real products and help shape how the world computes.

Job Summary

We are seeking an experienced verification engineer with robust expertise in SystemVerilog/UVM and/or C/C++-based verification to drive the verification of high-speed interconnect and memory IPs for advanced chiplet-based architectures. The ideal candidate will have hands-on experience in IP- and subsystem-level verification, with a strong focus on PCIe, CXL, UCIe, Ethernet, and DDR/memory controller verification. The role will involve protocol-level validation, coherency, cache and memory systems, and die-to-die communication.

Technical Skills & Expertise

- Strong experience developing UVM-based verification environments from scratch.
- Ability to create comprehensive verification plans and develop testbenches tailored to assigned IP, SubSystem, or functional domain.
- Hands-on experience verifying PCIe, CXL, UCIe, Ethernet, and DDR/memory controller IPs.
- Strong architectural and protocol-level knowledge of UCIe, PCIe, CXL, Ethernet, and DDR IPs, including working knowledge of FDI and RDI interfaces.
- Hands-on experience with industry-standard verification, simulation, and debug tools such as Questa, VCS, and Visualizer.




- Strong experience with constrained-random stimulus, functional coverage, and assertion-based verification methodologies.
- Knowledge of chiplet architectures and die-to-die communication.
- Strong understanding of coherency protocols and cache/memory systems.

What You'll Drive & Bring to the Role

- Partner with architects and RTL design teams to understand high-level system requirements, architecture, and specifications.
- Develop verification environments and reusable bus functional models, stimulus generators, checkers, assertions, trackers, and coverage metrics.
- Execute verification plans, including design bring-up, DV environment setup, regression execution, feature validation, and debug of test failures.
- Support post-silicon bring-up and debug activities.
- Track and communicate verification progress using key metrics such as test plan status, bug tracking, regression results, and coverage reports.
- Collaborate cross-functionally with design, architecture, firmware, and system teams to identify and resolve complex verification issues.

Required Qualifications

- Bachelor’s or Master’s degree in Electrical Engineering/Electronics Engineering/Computer Science Engineering.
- 8–12 years of work experience.

Why Join Us?

Own. Innovate. Make an Impact.

Join a talented team building next-generation compute solutions and working on cutting-edge AI and semiconductor technology. Take ownership, collaborate with exceptional engineers, expand your technical expertise, and make a meaningful impact in a culture that values innovation, collaboration, and teamwork.

Benefits

- Competitive Compensation: Compensation aligned with industry benchmarks.
- Comprehensive Health Insurance: Health coverage for employees and eligible dependents.
- Stock Options & Ownership Opportunities: Participate in the company’s growth through equity ownership opportunities.

📌 ASIC Design Verification - IP Verification (Bengaluru)
🏢 Tsavorite Scalable Intelligence
📍 Bengaluru