Role Description
Who we are:
At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 30+ countries, we build for boundless impact—touching billions of lives in the process. Visit us at .
Summary
UST is looking for an Analog Layout Engineer with strong expertise in FinFET-based analog/IO layout design and sign-off verification.
The Chance
We are looking for a skilled Analog Layout Engineer to drive the physical implementation of high-performance analog and IO circuits in advanced process technologies. This role requires hands-on experience in critical analog block layouts, deep understanding of layout-dependent effects, and ownership of layout execution from floorplanning through sign-off.
Key Responsibilities
• Design and implement high-quality layouts for critical analog and IO blocks such as LDOs, Bandgaps, Oscillators, and related circuits
• Perform full-custom analog layout development in advanced FinFET technologies
• Execute top-level floorplanning and hierarchical layout integration methodologies
• Ensure layout quality through DRC, LVS, Antenna, ERC, PERC, and other physical verification checks using Calibre tools
• Perform parasitic extraction and analysis using StarRC and support post-layout optimization
• Analyze and mitigate EMIR and self-heating effects to ensure robust silicon performance
• Apply layout best practices for matching, electromigration (EM), ESD protection, latch-up prevention, coupling, and crosstalk mitigation
• Collaborate closely with analog designers to understand circuit requirements and optimize layout implementation
• Drive layout reviews, sign-off activities, and design quality improvements
• Support tape-out activities and resolve physical design issues across the project lifecycle
Required Qualifications
• Bachelor's or Master's degree in
📌 Associate III (Bengaluru)
🏢 UST
📍 Bengaluru