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THE ROLE:
We are seeking an experienced Full Chip SoC Timing Lead in ASIC/SoC design implementation and timing closure. The ideal candidate will lead full-chip timing activities from synthesis through place-and-route, signoff, and tapeout for complex SoCs in advanced technology nodes. This role requires deep expertise in STA, timing constraints, MMMC flows, SI/crosstalk analysis, ECO closure, and cross-functional collaboration with RTL, PD, CTS, DFT, power, and signoff teams.

THE PERSON:
You have excellent communication and presentation skills,



demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Lead full-chip timing closure for complex SoC/ASIC designs across all modes and corners.
• Own and drive timing signoff from synthesis to final tapeout.
• Develop, validate, and maintain timing constraints including SDC for full-chip and block-level integration.
• Perform and review static timing analysis (STA) for setup, hold, recovery, removal, clock gating, and async paths.
• Drive MMMC timing methodology and ensure robust timing convergence across PVT corners.
• Work closely with physical design teams on floorplanning, placement, CTS, routing, and post-route timing optimization.
• Analyze an

📌 Lead Full-chip STA and timing signoff Engineer (Bengaluru)
🏢 Advanced Micro Devices
📍 Bengaluru