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THE ROLE:
The focus of this role is to build, execute, and sign off on the Power and EMIR closure for the IP/Full chip SOC

THE PERSON:
The candidate to have a passion for complex processor architecture, digital design, and verification in general. The candidate should be team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. The candidate should have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:




• EMIR closure at Tile /Partition/Subsytem/SOC levele on a particular node
• Drive Power and EMIR closure for design blocks and full-chip integration.
• Align EMIR analysis phases with PD milestones .
• Ensure compliance with signoff limits provided by SIPI team for given technology node
• Ability to analyze EMIR violations and propose implementation choices.
• Familiarity with DFx and scan architecture for EMIR considerations
• Technical Leadership• • Define EMIR signoff strategy, including IR drop and electromigration analysis.
• Review floorplan, clocking, and bus structures for IR hotspots.
• Coordinate bump allocation and power rail alignment with integration teams.

• Ownership of EMIR Flow & Signoff
• Collaboration & Coordination

• • • Work closely with block owners, PD team, and integration team to execute EMIR runs.
• Conduct EMIR run reviews and debug sessions

📌 Lead Full chip EM/IR analysis Engineer (Hyderabad)
🏢 Advanced Micro Devices
📍 Hyderabad