This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a SoC verification based in India.

This role offers the prospect to take end-to-end ownership of verification for complex digital design blocks within advanced ASIC projects. You will build verification environments from the ground up using SystemVerilog and UVM, covering testbench infrastructure, sequences, agents, scoreboards, and functional coverage. The position combines hands-on verification execution with sophisticated debugging, regression management, and coverage closure. You will work on high-performance networking silicon and interconnect technologies, with exposure to protocols such as UCIe, PCIe, and Ethernet. Collaboration with engineering teams will be essential to align block-level verification with broader system-level infrastructure. The role suits an experienced verification engineer who can work independently while contributing effectively in a customer-facing environment.
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Accountabilities:





• Take technical ownership of verification for 4–5 complex design blocks within each project and drive them toward verification sign-off.

• Build and maintain complete verification environments, including testbench infrastructure, agents, test sequences, scoreboards, and functional coverage models.

• Develop verification components from scratch using SystemVerilog and UVM.

• Execute directed and constrained-random testing across complex digital designs.

• Debug verification failures, analyze waveforms, investigate protocols, and perform root-cause analysis.

• Drive functional and code coverage closure and manage regression triage.

• Apply protocol knowledge to verify complex architectural features involving technologies such as UCIe, PCIe, and Ethernet.

• Collaborate with customer engineering teams and internal project leads to align block-level verification with top-level testbench infrastructure.

• Use industry-stand

📌 SoC verification (India)
🏢 Jobgether
📍 India