Minimum Qualification Required: B.E./B.Tech in Electronics, M.Tech
Candidate Skill: Digital & Analog Circuits Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Solid understanding of digital, analog and CMOS circuit concepts.
Candidate Skill: SystemVerilog & UVM Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Develop and maintain UVM-based verification environments and testbenches.
Candidate Skill: Verilog Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: RTL modeling, functional verification and simulation.
Candidate Skill: CMOS Concepts Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Apply CMOS design concepts in digital and mixed-signal verification.
Candidate Skill: Pre-Silicon Verification Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Perform block,
subsystem and full-chip pre-silicon verification.
Candidate Skill: Gate Level Simulation (GLS) Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Execute GLS for timing and functional validation.
Candidate Skill: SystemVerilog Assertions (SVA) Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Develop assertions and verify protocol and functional behavior.
Candidate Skill: Debug & Root Cause Analysis Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Analyze waveform failures and resolve verification issues.
Candidate Skill: Regression Execution & Optimization Years of Experience/Expectations: Minimum 5 years Mandatory/Optional: Mandatory Description of Work: Manage regression runs and optimize verification flow.