Position: Design Verification Engineer (SystemVerilog/UVM) (BB50FT RM 4458)

• Candidate Skill: IP/Block/Subsystem Verification, RTL Front-End Verification
• Years of Experience/Expectations: Minimum 5 Years
• Mandatory/Optional: Mandatory
• Candidate Skill: SystemVerilog (SV), UVM Verification, UVM Testbench Development
• Years of Experience/Expectations: Minimum 4 Years
• Mandatory/Optional: Mandatory
• Candidate Skill: AXI, AHB Interfaces, Bus Protocol Verification
• Years of Experience/Expectations: Minimum 2 Years
• Mandatory/Optional: Mandatory
• Candidate Skill: PCIe, NVMe Protocol Verification
• Years of Experience/Expectations: Minimum 1 Year
• Mandatory/Optional: Mandatory
• Candidate Skill: Perl, Python Scripting, Verification Automation
• Years of Experience/Expectations: Minimum 1 Year
• Mandatory/Optional: Optional

Job Description

• An expert level experience with PCIe IP/sub-systems.
• AXI protocol is mandatory
• Highly experienced with defining block, sub-system.




• An expert level with developing UVM-based SV test-benches.
• Deep understanding and knowledge of verification methodologies flows and quality metrics.
• Excellent debugging and problem-solving skills.
• Team player with great interpersonal communication skills.

Job Qualifications

• At least 3-6 years of relevant experience in PCIe verification.
• Strong and relevant expertise with ASIC simulation tools and advanced verification methods.
• Expert level in verification languages such as UVM and System Verilog.
• Relevant experience with writing block-level .
• Education: B.S. in electrical engineering, computer science with extensive industry experience.

Skills Required

• IP/Block/Subsystem Verification (RTL Front end verification) – minimum 5 years
• SV, UVM Verification – minimum 4 Years
• Interfaces (AXI/AHB) – minimum 2 years
• Protocols (DDR/Onfi/PCIE/NVMe) – minimum 2 years
• Scripting (Perl/Python) – Optional

📌 Design Verification Engineer (Hyderabad)
🏢 Source right
📍 Hyderabad