Job Description: Simulation Migration Engineer(SV/UVM)
Experience: 5 Years
Location: Hyderabad
Key Requirements:
• Strong hands-on experience in SystemVerilog (SV) and UVM methodology
• Experience in simulation migration activities, specifically from VCS to Xcelium (Exilium)
• Good understanding of low power verification concepts
• Expertise in functional verification, including testbench development and execution
• Solid skills in coverage analysis (functional & code coverage)
• Proficient in debugging simulation issues and regression failures
• Experience in verification environment bring-up and migration support
📌 RTL Engineer (Hyderabad)
🏢 Cyient
📍 Hyderabad
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.