Lead Physical Design Engineer (Bengaluru)

Lead Physical Design Engineer (Bengaluru)

02 Oct
|
Leadsoc Technologies
|
Bengaluru

02 Oct

Leadsoc Technologies

Bengaluru

Lead Physical Design Engineer – 8+ Years

Location: Bengaluru
Experience: 8+ Years
Notice Period: Immediate to 30 Days preferred
Employment Type: Full time

Job Summary
We are looking for an experienced Lead Physical Design Engineer with 8+ years of strong hands-on experience in VLSI Physical Design. The candidate will own complex block/full-chip implementation activities and drive timing, power, performance, area, and physical signoff closure.

Key Responsibilities
• Own and drive end-to-end Physical Design implementation from netlist to GDSII.
• Lead floorplanning, power planning, placement, CTS, routing, optimization, and signoff activities.
• Drive timing closure across multiple modes and corners.
• Analyze and resolve complex setup, hold, congestion, clock, and routing issues.
• Drive PPA optimization throughout the implementation cycle.
• Lead ECO implementation and closure.
• Drive resolution of DRC, LVS, antenna, density, IR/EM, and other signoff issues.
• Work on advanced-node and high-performance SoC designs.
• Collaborate closely with STA, RTL, Synthesis, DFT,



Power/IR-EM and Physical Verification teams.
• Drive methodology and flow improvements to improve implementation quality and productivity.
• Develop automation using Tcl/Perl/Python.
• Provide technical guidance and mentorship to junior and senior engineers.
• Participate in technical reviews, root-cause analysis, and project planning.
• Take ownership of project deliverables and drive issues to closure.

Required Skills
• 8+ years of relevant experience in VLSI Physical Design.
• Strong expertise in complete Physical Design implementation and signoff.
• Hands-on experience with one or more of:
• Cadence Innovus
• Synopsys Fusion Compiler
• Synopsys ICC2
• Strong knowledge of:
• Floorplanning & Power Planning
• Placement Optimization
• CTS & Clock Optimization
• Routing
• MMMC
• STA & Timing Closure
• PPA Optimization
• ECO
• Physical Signoff
• IR/EM
• Experience with Low Power / Multi-Voltage desig

📌 Lead Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru

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