10+ years of experience in SoC PnP Architecture within the semiconductor industry, with a strong track record of driving system-level performance, power, and efficiency investigations across complex silicon platforms.
Solid expertise in SoC performance architecture and pre-silicon performance analysis, including:
• Hands-on experience with simulation and hardware emulation platforms such as Palladium, Veloce, ZeBu, or equivalent
• Performance analysis using cycle-accurate, transaction-level, and emulation-based environments
• Waveform-based debug and signal-level performance analysis
• Latency, bandwidth, throughput, QoS, and utilization characterization
• Transaction-level tracing and protocol debug across CHI, AXI, PCIe, CXL, or equivalent system protocols
• Identification of system-level bottlenecks across compute, interconnect, memory, and IO subsystems
• Architectural tradeoff analysis across performance, power, area, latency, bandwidth, and implementation complexity
Strong experience with SOC Performance and Power modeling methodologies, including:
• Development and use of SystemC/TLM, analytical, trace-driven architecture models
• Building and calibrating models for performance, power, latency, bandwidth, utilization, and efficiency analysis
• Model-to-silicon correlation, including alignment of pre-silicon projections, emulation results, and post-silicon measurements
• Early-stage architecture exploration to evaluate performance, power, area, thermal, TDP, and efficiency tradeoffs
• Using models to guide SoC architecture decisions, IP configuration, memory/interconnect sizing, QoS strategy, and platform-level optimization
• Ability to translate modeling insights into clear architectural recommendations and measurable product improvements
Extensive Experience In Post-silicon Performance And Power Characterization, Including
• Silicon bring-up support from a performance and PnP perspective
• Performance counter, PMU, telemetry, and trace-driven investig
📌 SoC PnP Architect (Bengaluru)
🏢 ARM
📍 Bengaluru