JOB DESCRIPTION

Title/Position: Senior RTL Design Engineer
Location: Bangalore, Hyderabad
Experience: 5 to 15 Years
Mail ID- [email protected]
Type: Fulltime

Key Skills and Responsibilities:
• Microarchitecture, Module design and simulation
• Digital design, implementation and integration – RTL Coding, Lint, CDC, and Synthesis.
• Develop design constraints and coordinate to debug both functional and DFT test issues.
• Synthesis and P&R; constraint generation, including clock tree specification
• Scan insertion and pattern generation
• Support IP/Design Verification/Firmware/Software System to provide the necessary support for timely closure of assigned blocks design and implementation issues.

Job Requirements
• Digital design knowledge:
• Verilog coding
• Register file design
• Serial interfaces
• Interconnect fabrics
• State machine architecture
• Clock domain crossing
• Scan and self-test
• Synthesis, Linting, STA
• Automation scripting and design flows
• Verification, including System Verilog knowledge




• Low power design, Power intent specification and validation methodology.
• Battery management and RISC-V based Subsystems/SOCs.
• Knowledge of TFM (Tools, Flows and Methodologies) flows: Simulation, Lint, CDC/RDC and power intent checks UPF.
• Familiarity with Cadence, Synopsis design tools
• Ability to work as part of a team and with low levels of supervision

About us:
Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service
Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless,
Automotive and Embedded Solutions.
Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an effective turnkey solution for silicon bring-up, spec to the product. With 2500+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tesso

📌 Senior RTL Design Engineer (India)
🏢 TESSOLVE
📍 India