03 Oct
|
Quest Global
|
Bengaluru
03 Oct
Quest Global
Bengaluru
Job Requirements
• Design and implementation of UVM/SystemVerilog verification environments (checkers, trackers, scoreboards, assertions, functional coverage).
• Creation of test plans and test cases to exercise design features and drive code/functional coverage closure.
• Running regressions, analyzing failure signatures, debugging issues, and coordinating fixes with design and emulation teams.
• Collaboration with system architects and cross-functional teams on feature verification and debug activities.
• Verification of interconnect and bus protocol behavior (CHI/AHB/AXI/ACE/ACE-Lite) and related system interactions..
📌 Senior Engineer RISC (Bengaluru)
🏢 Quest Global
📍 Bengaluru