We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent a decade or more in verification and you know that formal is not a checkbox, it is the difference between finding a corner case bug in week two or in production six months later. You walk into a customer site, look at their design blocks and test benches, and see the problem underneath the symptoms. You ask questions that get to root cause, not surface noise.
You have debugged enough performance bottlenecks to know when the issue is the tool, the model, or the design itself, and you can explain the tradeoff in terms the design team will understand.
You are comfortable presenting to senior engineers and equally comfortable rolling up your sleeves to optimize a formal test bench that is choking on state space explosion.
At Synopsys, you will work directly with customers building the most complex chips in the industry, and what you recommend will shape how they verify their designs.
What You'll Be Doing
• Lead technical deployment of VC Formal solutions at customer sites, assessing verification environments and recommending formal methodologies tailored to their design challenges
• Analyze customer design blocks to identify the right targets for formal property checking, sequential equivalence checking, formal coverage analysis, and connectivity checking
• Diagnose root causes of tool performance issues, including state space explosion and convergence problems, then optimize formal test benches to achieve proof closure
• Develop and deliver technical training