Descriptions & Requirements

Job Description and Requirements

We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are
You have spent years building digital logic that has to actually work in silicon, not just pass simulation, actually work, at 600MHz+ clock speeds with real area budgets and power constraints that matter. You know that the difference between an IP core that ships and one that gets redesigned is usually a micro-architecture decision made during spec review, and you are the kind of engineer who catches that decision before it becomes a six-month debug cycle.
You are comfortable moving between protocol specs like PCIe Gen5 or Ethernet 400G and the actual RTL that implements them,



translating pages of standards documents into data paths that close timing and control logic that handles every corner case. You do not need a perfect specification to get started. You ask the right questions, sketch out the architecture, and find a way through ambiguity without creating technical debt downstream.
You like hard problems. Reed Solomon FEC engines, MAC SEC pipelines, CDC domains that cross multiple clock regions, these are not obstacles, they are the work. You have debugged synthesis mismatches at 2am, you have rewritten a critical path to shave 200ps, and you have mentored someone through their first timing closure. At Synopsys, you will work on DesignWare IP cores that power everything from automotive SoCs to enterprise data centers. The team is global, the RTL is real, and what you build will ship in millions of devices.
What You'll Be Doing
• Architect and implement RTL designs fo

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