We are seeking an experienced Staff ASIC/SoC Verification Engineer to join our
agile and fast‑paced engineering team. In this role, you will be responsible
for ensuring the functional correctness, robustness, and overall quality of our
cutting‑edge semiconductor and SoC designs. If you thrive in a collaborative
environment and enjoy solving complex technical challenges, this opportunity is
an excellent fit.
LI-VS1
RESPONSIBILITIES
Responsibilities:
1. Verification Planning and Execution:
* Develop and execute comprehensive verification plans.
* Close verification with coverage closure, ensuring high-quality results.
* Apply standard ASIC verification techniques, including test planning,
testbench creation, code and functional coverage, directed and random
stimulus generation, and assertions.
2. Testbench Development:
* Create and enhance testbenches using SystemVerilog (OVM/UVM) or other
standard testbench languages.
* Implement reusable Verification IP (VIP) components.
* Collaborate with third-party VIP providers.
3.
Methodology and Flows:
* Demonstrate a solid understanding of ASIC design and verification
methodologies.
* Apply object-oriented programming principles effectively.
* Implement constraint random verification methodology.
4. Technical Skills:
* Proficiency in SystemVerilog (OVM/UVM) and other relevant languages
(C/C++, Perl, Tcl, Python, Verilog PLI).
* Familiarity with industry standards (e.g., I2C/SPI).
* Experience with low-power verification using UPF (Unified Power Format) is
a plus.
* Knowledge of formal verification techniques is advantageous.
5. Collaboration and Communication:
* Work effectively with internal teams and external customers.
* Strong written and verbal communication skills.
* Initiative, analytical problem-solving abilities, and adaptability within
a diverse team environment.