Responsibilities
Architect, implement, and validate creative DFT techniques on ARM SoCs. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.
Required Skills And Experience
Core DFT skills considered for this position should include some of the following: Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics
Experience ranges from 3- 20 Years.
Experience coding Verilog RTL, TCL and/or Perl
Proficient in Unix/Linux environments
Bachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering,
or a related field
“Nice To Have” Skills and Experience :
Familiarity with IEEE 1149, 1500, 1687, 1838
Synthesis & Static Timing Analysis
Familiarity with SoC style architectures including multi-clock domain and low power design practices.
Validated understanding of Siemens DFT tools
Familiarity with Arm IP like the following: Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug
Experience with 2.5D and 3D test
Ability to work both collaboratively on a team and independently
Hard-working and excellent time management skills with an ability to multi-task
An upbeat demeanor to working on exciting projects on the cutting edge of technology
Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools
Accommodations at Arm
At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, ple
📌 Senior Engineer (Bengaluru)
🏢 ARM
📍 Bengaluru