Architecture, Verification, Physical Design and STA teams . Perform
RTL simulation,
debugging and functional issue resolution . Support
lint, CDC, synthesis, STA and other design-quality checks . Analyze and resolve
timing, area, power and functional issues . Drive design closure and support integration of RTL blocks into larger SoC designs. Mentor junior engineers and contribute to RTL coding standards and design methodologies. Required Skills 7–20+ years
of experience in RTL Design / Digital Design. Strong hands-on experience with
Verilog/SystemVerilog . Solid understanding of
Microarchitecture and Digital Logic Design . Experience in designing complex
IP/SoC/subsystem blocks . Good understanding of
ASIC design flow
from specification to implementation. Strong knowledge of
RTL coding, synthesis, lint, CDC and STA . Experience with
PPA optimization and timing closure . Strong debugging and problem-solving skills. Experience working with cross-functional teams including
DV, Architecture and Physical Design
📌 Senior / Lead / Principal Rtl Design Engineer Mumbai
🏢 leadsoc technologies
📍 Mumbai
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.