We are looking for an experienced Analog Layout Engineer to join our semiconductor design team and work on high-performance analog and mixed-signal IPs in advanced CMOS/FinFET technology nodes.
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The ideal candidate should have solid hands-on experience in full-custom analog layout, preferably with TSMC technology nodes, and a solid understanding of matching, parasitics, advanced layout techniques, and physical verification.
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The role involves working closely with analog circuit designers, physical verification, and other cross-functional teams to deliver high-quality, silicon-ready layouts.
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Key Responsibilities
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Develop full-custom analog and mixed-signal layouts for complex IC designs.
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Work on layout of analog building blocks such as:
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Op-Amps
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Bandgap references
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LDOs / Regulators
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ADC/DAC blocks
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PLL/DLL
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Charge Pumps
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Current/Voltage References
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High-speed I/O and SerDes/DDR PHY circuits
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Implement advanced layout techniques including:
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Common-centroid
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Interdigitation
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Symmetry
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Matching
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Dummy devices
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Guard rings
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Shielding
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Sensitive-node isolation
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Perform parasitic-aware layout optimization and minimize the impact of routing and device parasitics on circuit performance.
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Work closely with analog designers to understand circuit requirements and translate schematics into optimized physical layouts.
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Perform DRC, LVS, ERC and other physical verification checks and debug layout issues.
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Support PEX/post-layout simulation and optimize layouts based on extracted parasitics.
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Ensure layouts meet requirements for area, matching, noise, reliability, EM/IR and performance.
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Work with advanced TSMC technology nodes, including FinFET-based processes.
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Collaborate with circuit design, verification, reliability,
📌 Analog Layout Engineer Bengaluru (India)
🏢 Leadic Design
📍 India
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