- Noida, Bangalore and Hyderabad
Desired Skills:
- Hands-on experience with focus on front-end complex RTL design involving logic IP design.
- Effective in Coding in Verilog
- Creating testbenches in Verilog or UVM
- Running simulations using ncsim, vcs or similar tools
- Debugging design issues using waveform viewers
- Creating SDC and UPF constraints for synthesis.
- Understanding timing reports.
- Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation)
- Highly motivated and skillful at solving difficult technical problems
- Experience with scripting in Perl/Python/Shell
Experience : 2 to 4 Years
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Subject : Mention your Domain and Exp
Email :
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📌 Design Engineer-RTL (Noida)
🏢 Keen Heads
📍 Noida