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MTS Silicon Design Engineer – PTPX Power Engineer
Role Summary
Responsible for power analysis, power optimization, and signoff of complex SoC/IP designs using PrimeTime PX (PTPX) and related power methodologies. The engineer will drive energetic and leakage power convergence, identify power bottlenecks, develop power reduction strategies, and collaborate across PD, RTL, Architecture, Timing, DFT, and Power teams to achieve product power targets.
Key Responsibilities
• Perform block, tile, and full-chip power analysis using PrimeTime PX (PTPX).
• Analyze dynamic, leakage, clock, memory, and switching power components to identify optimization opportunities.
• Drive power convergence across project milestones and signoff stages.
• Correlate power across RTL, synthesis, implementation, and silicon projections.
• Debug high-power hotspots and recommend architecture, RTL, clocking, and physical design optimizations.
• Execute power regression flows and generate power dashboards, reports, and trend analysis.
• Collaborate with PD, timing, clocking, and RTL teams to implement power-reduction solutions.
• Develop automation, scripts, and methodologies to improve power analysis efficiency and accuracy.
• Support power signoff reviews and customer-facing power deliverables.
Required Qualifications
• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Computer Engineering, or related field.
• 7 to 1
📌 PTPX Power/PNR Engineer (Bengaluru)
🏢 AMD
📍 Bengaluru