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MTS Silicon Design Engineer – Tile PnR
Role Summary
Responsible for end-to-end physical implementation and convergence of complex SoC/IP tiles. The engineer will drive floorplanning, place-and-route, timing closure, power and area optimization, physical verification readiness, and ECO implementation while collaborating closely with RTL, architecture, CAD, timing, clocking, and full-chip teams. Expected to independently own critical tiles, deliver high-quality milestones, and contribute to methodology and automation improvements.
Key Responsibilities
• Own end-to-end implementation and convergence of assigned tiles from netlist handoff to signoff.
• Drive floorplanning, placement, CTS, routing, timing, power, congestion, and area optimization.
• Perform timing analysis and implement setup/hold/ECO fixes to achieve QoR targets.
• Debug implementation issues related to timing, congestion, DRC, EMIR, CDC, and physical integration.
• Collaborate with RTL, Architecture, Clocking, DFT, Integration, and CAD teams to resolve design challenges.
• Support milestone deliveries and ensure quality execution aligned with project schedules.
• Develop automation, scripts, and improved methodologies to enhance productivity and convergence efficiency.
• Mentor junior engineers and contribute to technical reviews, best practices, and knowledge sharing.
Required Qualifications
• Bachelor’s or Master’s degree in Electrical/Electronics Enginee
📌 PD PNR Engineer (Bengaluru)
🏢 AMD
📍 Bengaluru