04 Oct
|
Leadic Design
|
Hyderabad
04 Oct
Leadic Design
Hyderabad
Hiring PCIe & GLS Verification Engineers with 4+ years of experience in SystemVerilog/UVM. Experience in PCIe Gen5, GLS, RTL verification, assertions, coverage, debugging, and protocol verification preferred.
📌 Design and Verification Engineer (Hyderabad)
🏢 Leadic Design
📍 Hyderabad