Position: Mixed-Signal Co-Simulation Engineer (BB46FT RM 4457)

Key Responsibilities

• Run full-chip or block-level mixed-signal co-simulations using Cadence AMS Designer/Xcelium or Synopsys VCS.
• Develop behavioral analog models using Verilog-AMS, Verilog, and SystemVerilog Real Number Modeling (RNM/wreal).
• Build metric-driven verification settings using SystemVerilog and UVM-AMS.
• Debug analog and digital interface issues, waveform anomalies, simulation convergence failures, and drive functional coverage closure.
• Develop automation scripts in Python, Perl, or Tcl for verification flows, regression management, and reporting.
• Create and execute verification plans to validate behavioral models against transistor-level schematics.




• Configure and execute mixed-mode simulations with selected blocks running at schematic/SPICE level while the remaining design uses behavioral models.

Required Skills And Qualifications

• SystemVerilog, UVM, Verilog, Verilog-AMS, and SystemVerilog RNM (wreal)
• Mixed-signal verification and co-simulation experience
• Knowledge of PLL, DLL, DCC, ADC, DAC, LDO, Bandgap, and ZQ Calibration
• Experience with Cadence Virtuoso, Spectre, Xcelium, Cadence AMS Designer, or Synopsys VCS
• Robust hands-on experience in mixed-signal/AMS verification.

📌 Mixed Signal Co Simulation Engineer Hyderabad
🏢 Source right
📍 Hyderabad