Role Overview

The focus of this role is to build, execute, and sign off on the Power and EMIR closure for the IP/Full chip SOC

The Person

The candidate to have a passion for complex processor architecture, digital design, and verification in general. The candidate should be a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. The candidate should have solid analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities
EMIR closure at Tile /Partition/Subsytem/SOC levele on a particular node
Drive Power and EMIR closure for design blocks and full-chip integration.
Align EMIR analysis phases with PD milestones .
Ensure compliance with signoff limits provided by SIPI team for given technology node
Ability to analyze EMIR violations and propose implementation choices.
Familiarity with DFx and scan architecture for EMIR considerations
Technical Leadership
Define EMIR signoff strategy, including IR drop and electromigration analysis.
Review floorplan, clocking, and bus structures for IR hotspots.




Coordinate bump allocation and power rail alignment with integration teams.
Ownership of EMIR Flow Signoff
Collaboration Coordination
Work closely with block owners, PD team, and integration team to execute EMIR runs.
Conduct EMIR run reviews and debug sessions with stakeholders.
Methodology Flow Development
Maintain and improve EMIR flow
Engage with SIPI team for current profile analysis and probe pad/interposer runs.

Academic Credentials
Bachelors or Masters degree in Electrical Engineering

Preferred Experience
Minimum 7 to 10 years of relevant work experience.

Skills
EMIR
Power signoff
DFx and scan architecture
IR drop and electromigration analysis
Signoff tools: Redhawk_Sc, Voltas, PT-PX, Primetime
Synthesis and PD flows (ICC2/FC, Fusion Compiler)
Scripting (Shell, Python, Perl, TCL)
AI technologies in day to day problem solving
Technical leadership

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Lead Full Chip Em/ir Analysis Engineer Hyderabad (India)
🏢 Advanced Micro Devices (AMD)
📍 India