Job DescriptionIn this role, you will own and drive Design for Test (DFT) strategy, architecture, and implementation across the full chip lifecycle.
nResponsibilities
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Execute and support Design-for-Test (DFT) activities, including Scan Insertion, ATPG, and OCC Integration.n
Perform DRC debugging, test coverage analysis, and simulation debugging across different stages of the DFT flow.n
Analyze and resolve issues related to testability, fault coverage, and pattern generation.n
Work with advanced DFT methodologies such as SSN, IJTAG, ICL, and PDL.n
Collaborate with cross-functional teams to ensure seamless DFT integration and productive issue resolution.n
Drive continuous improvements in DFT flows, methodologies, and debugging efficiency.n
Experience: 3 to 8 yrsn

nRequired Skills: Key Responsibilities:
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Define and implement DFT architecture for large, complex SoCs/ASICsn
Own end-to-end DFT strategy and execution including Scan, ATPG, MBIST, LBIST, JTAG, and Boundary Scann
Perform Scan insertion, ATPG pattern generation, compression,



and fault gradingn
Develop and maintain DFT specifications and ensure compliance throughout the design cyclen
Integrate and verify DFT logic at RTL and gate-level (GLS)n
Collaborate with verification teams for pattern simulation, validation, and debugn
Work closely with physical design teams to meet timing, power, and area constraintsn
Debug silicon bring-up issues and support ATE test pattern validationn
Drive improvements in DFT methodologies and flowsn
Mentor junior engineers and provide technical leadershipn
Robust expertise in Scan, ATPG, BIST (MBIST/LBIST), JTAG/Boundary Scan, and compression techniquesn
Hands-on experience with DFT tools such as Synopsys DFT Compiler, Tetramax, Tessent, or equivalentn
Solid understanding of RTL design, synthesis, and verification flowsn
Familiarity with STA and physical design constraints related to DFTn
Experience in

📌 Dft Engineer Hyderabad (India)
🏢 SmartSoC Solutions
📍 India