Role Overview

We are seeking an experienced Physical Design Manager to lead Physical Design and CAD teams responsible for end-to-end ASIC/SoC physical implementation.

The role requires robust technical depth in full-chip Physical Design, advanced technology nodes, STA/timing closure, physical signoff, low-power implementation, and tapeout, combined with proven people-management experience. The position will work closely with Architecture, RTL, DFT, Analog/Mixed-Signal, Packaging, and Program Management teams.

Key Responsibilities
Lead and manage Physical Design and CAD teams across multiple locations.
Own end-to-end ASIC/SoC physical implementation from netlist to GDSII/tapeout.
Drive floorplanning, power planning, placement, optimization, CTS, routing, and post-route optimization.
Lead STA and timing closure across multiple modes and corners.
Drive physical signoff including signal integrity, IR drop, electromigration (EM), DRC, LVS, and low-power verification.
Provide technical direction for complex advanced-node ASIC/SoC designs.




Lead implementation of low-power architectures, including DVFS, power gating, multi-voltage domains, UPF/CPF, and power-aware flows.
Collaborate with Architecture, RTL, DFT, Analog/Mixed-Signal, Packaging, and Program Management teams to resolve implementation and integration issues.
Drive EDA methodology, flow development, automation, and tool optimization using Synopsys and/or Cadence platforms.
Review design quality, implementation metrics, timing, power, area, congestion, and signoff readiness.
Support advanced packaging and chiplet-based implementation flows where applicable.
Mentor technical leads and engineers, manage team capacity, and drive execution against project and tapeout schedules.

Required Qualifications
B.Tech / M.Tech in Electronics, Electrical Engineering, VLSI, Microelectronics, or a related discipline.
12–20 years of experience in ASIC/SoC Physical Design and physical implementation.

📌 Physical Design Manager Bengaluru
🏢 Best NanoTech
📍 Bengaluru