We are looking for experienced Design Verification Engineers with strong hands-on expertise in SoC verification.

Key Responsibilities

- Develop SoC-level verification plans and UVM environments.
- Create test cases, sequences, assertions, scoreboards and coverage models.
- Perform subsystem- and SoC-level verification.
- Develop C/C++-based, processor-driven tests.
- Debug simulation failures and drive coverage closure.
- Collaborate with design, architecture, firmware and validation teams.

Required Skills

- Minimum 4 years of relevant Design Verification experience.
- Strong SoC verification experience.
- Proficiency in SystemVerilog and UVM.
- Knowledge of SoC architecture, processors, memories, interrupts, clocks and resets.
- Experience with AXI, AHB, APB, PCIe, DDR,



SPI, I2C, UART or Ethernet.
- Strong debugging, functional coverage and code coverage experience.
- Knowledge of Python, Perl, Tcl or Shell scripting is preferred.

Significant: Candidates with less than 4 years of experience will not be considered. This position is not open to interns, freshers or entry-level candidates.

Interested candidates can share their updated resumes at:

[email protected]
[email protected]

Pay: ₹1,200,000.00 - ₹2,004,263.11 per year

Work Location: In person

📌 Senior Design Verification Engineer (Bengaluru)
🏢 Chiplogic Technologies
📍 Bengaluru