About the role
We are seeking an experienced to own the end-to-end testing, characterization, and failure analysis strategy for complex, next-generation multi-die packages.
You will own the complete Post Silicon validation lifecycle across a multi-die architecture—covering high-speed die-to-die (UCIe) interconnects, Power Delivery Networks (PDN/PMIC), Platform Management Controllers (PMC), PCIe/CXL subsystems.
Additionally, you will apply statistical analysis and machine learning to test data—driving outlier detection, bench-to-ATE correlation, and predictive telemetry signals—without treating ML models as a substitute for true physical root-cause analysis.

What you’ll do
Test content and automation
Test Plan Ownership: Define development test strategies, coverage targets, content architecture, and strict traceability from architectural requirements to validation evidence.
Bare-Metal & C/Python Test Content: Write low-level C and Python test suites—including bare-metal exercisers, traffic generators, stress patterns, and custom firmware drivers/hooks.




Scalable Automation & HIL: Build robust test frameworks featuring instrument control, automated sequencing, structured result capture, and Hardware-in-the-Loop (HIL) CI/CD integration for continuous validation.
Bench-to-ATE Handoff: Develop lab-to-ATE correlation test suites and drive smooth handoffs to Product & Test Engineering (PTE)
Own the development test plan: coverage goals, content architecture, and the traceability between a requirement, the test that exercises it, and the evidence it passed.

Characterization and margin
Injection Frameworks: Build minimally invasive fault-injection hardware/software infrastructure that perturbs target datapaths without destabilizing the test setup itself.
Protocol & Platform Fault Testing: Execute rigorous error campaigns targeting CRC retries, lane degradation/repair, sideband timeouts, PCIe AER, DMA/IOMMU translation faults, and PMIC reset conditions.
Firmw

📌 Staff Engineer Bengaluru
🏢 tylsemi
📍 Bengaluru