Responsibilities

We are seeking an experienced Sr. Staff Physical Design Engineer to lead end‑to‑end physical design for complex SoCs and large digital blocks. The role involves ownership of floorplanning, placement, CTS, routing, timing closure, and physical sign‑off across MMMC scenarios.
You will drive STA, IR/EM, power integrity, and DRC/LVS sign‑off, support ECOs, and enhance P&R; methodologies through automation. Close collaboration with RTL, STA, DFT, and verification teams is key, along with mentoring junior engineers. You will focus on:

Physical Design & Implementation
Own end‑to‑end place‑and‑route execution for complex SoCs and large digital blocks
Perform floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
Drive timing closure across multi‑mode, multi‑corner (MMMC) scenarios
Solve challenging setup/hold, clocking, and CDC‑related timing issues

Sign‑off & Quality Closure
Perform static timing analysis (STA) and constraint debugging at block and full‑chip level
Lead IR drop, EM, and power integrity analysis,



and implement corrective actions
Execute and debug physical verification (DRC/LVS) to achieve clean sign‑off
Support ECO flows, late‑stage fixes, and post‑layout optimization

Methodology & Automation
Develop, enhance, and maintain P&R; flow automation using Tcl, Python, Perl, and shell scripting
Improve turnaround time, QoR, and repeatability through methodology enhancements
Review and contribute to physical design guidelines and best practices

Cross‑Functional Collaboration
Work closely with RTL design, STA, verification, DFT, and architecture teams
Provide early physical feasibility feedback on clocking, floorplan, and RTL structures
Mentor junior engineers and act as a technical point of reference within the PD team

Qualifications
Bachelor’s degree or Master’s in Electrical / Electronics Engineering or related field
7+ years of experience in ASIC physical design
Proven track record of

📌 Senior Staff Physical Design Engineer Bengaluru
🏢 MaxLinear
📍 Bengaluru