UST Job Title: Associate III - VLSI

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in over 25 countries, we build for boundless impact—touching billions of lives in the process. Visit us at .

The Prospect:

UST is looking for DFT Engineer

Responsibilities:
Scan & ATPG
Solid understanding of Siemens Tessent Tools for ATPG with SSN methodology
Experience in ICL, PDL, Stuck-at and transition fault pattern generation
Good understanding on scan coverage and experience in carrying out coverage analysis
Experience in Timing and no Timing gate level simulations and debugging simulation failures.
Experience in carrying out DFT DRC checks in RTL and analyzing the violations.
Strong understanding of Scan structures, IEEE1149.1, IEEE1687, ATPG methodology and flow.
Valuable understanding of timing constraints, synthesis flow and scan insertion using DC/FC




Strong TCL/scripting knowledge MBIST
Strong understanding of Siemens Tessent tools for MBIST insertion and verification
Experience in MBIST insertion in RTL, pattern generation.
Experience in ICL, PDL, IEEE1149.1, IEEE1687, MBIST verification and debugging simulation failures.
Good understanding of MBIST algorithms, architecture, and diagnosis features
Robust TCL/scripting knowledge Verification
Strong knowledge on ICL, PDL, IEEE1149.1, IEEE1687, Simulations tools such VCS
Experience in creation of DFT test bench structures, verifying DFX structures in RTL and debugging simulation failures
Good understanding of DFT structures such as scan controller, OCC, EDT, JTAG, iJTAG, IOs, HSIO loopback, reset controller.
Strong TCL/scripting knowledge

What we believe:

We’re proud to embrace the same values that have shaped UST since the beginning. Since day one, we’ve been building enduring relationships and a cultu

📌 Associate Iii Bengaluru
🏢 UST
📍 Bengaluru