This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding current and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for valuable. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
What You'll Do:
Define and architect high-performance blocks for the latest, most advanced networking ASICs
Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
Collaborate with the verification team in the development of the testplan and assist in debugging test failures
Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes
What You Need to Bring:
Strong Verilog RTL coding skills
Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
Knowledge of high-performance memory subsystems
Knowledge of multi-domain clock synchronization and high-speed serial interfaces
Robust problem solving and ASIC debugging skills
Excellent written and verbal communications skills
Strong leadership skill is a plus
MSEE or BSEE is required with 15 plus years of experience
Accessibility
HPE is committed to creating an inclusive and accessible workplace and encourages applications from al