Key Responsibilities
Perform SoC and subsystem-level verification for complex ASIC designs.
Develop and maintain verification environments using SystemVerilog and UVM.
Develop test cases, test scenarios, assertions, and functional coverage.
Verify and integrate multiple IPs at the SoC level.
Analyze simulation results and debug functional issues.
Work closely with Design, Architecture, and other Verification teams to identify and resolve issues.
Contribute to improving verification methodologies, quality, and coverage.
Required Skills
48 years of experience in ASIC/SoC Design Verification.
Solid hands-on experience with SystemVerilog and UVM.
Valuable programming knowledge in C/C++.
Experience in SoC-level verification with multiple IPs.
Valuable understanding of verification methodologies and debugging.
Knowledge of AXI or other standard on-chip protocols.
Exposure to one or more high-speed protocols is an added advantage.