We are looking for a highly motivated Design Verification Engineer with strong expertise in Gate-Level Simulation (GLS) to execute and debug GLS activities across IP, Subsystem, and SoC levels. The ideal candidate should have hands-on experience in GLS setup, execution, timing validation, failure analysis, and closure. The role requires excellent debugging capabilities, collaboration with cross-functional teams, and the ability to adapt quickly to customer-specific flows and methodologies.
Key Responsibilities
GLS Execution
• Setup, build, and execute Gate-Level Simulations across IP, Subsystem, and SoC levels.
• Support GLS activities across IPAR and MPAR validation environments.
• Run and analyze:
• Zero Delay Simulations
• SDF-Based Timing Simulations
• Power-Aware Simulations
• Drive simulation execution from environment setup through closure.
• X-Propagation issues
• RTL-to-Netlist mismatches
• Assertion failures
• Coverage failures
• Test failures
• Analyze waveform dumps and identify underlying design or implementation issues.
• Work closely with Design, STA, Physical Design, and Verification teams to resolve GLS failures.
Verification & Validation
• Perform failure triaging and closure of GLS issues.
• Support assertion-based verification and coverage analysis.
• Contribute to functional and timing signoff through comprehensive debug and verification activities.
• Ensure RTL and netlist behavioral consistency through detailed analysis.
Collaboration
• Work closely with cross-functional teams to drive issue resolution.
• Communicate debug findings and provide timely status updates.
• Quickly adapt to customer-specific tools, methodologies, and execution environments.
• Actively contribute as a team player in a quick-paced project environment.