We are looking for an experienced Design Verification Engineer with 6–10 years of hands-on experience in SystemVerilog and UVM-based verification. The ideal candidate will have solid experience verifying complex ASIC/SoC/IP designs and good knowledge of high-speed communication protocols, particularly Ethernet and PCIe.
Key Responsibilities:
- Develop and maintain SystemVerilog/UVM-based verification environments.
- Create test plans, test scenarios, test cases, and verification strategies.
- Develop UVM testbenches, sequences, drivers, monitors, scoreboards, and functional coverage.
- Perform functional, regression, and corner-case verification of IP/SoC designs.
- Debug RTL, simulation failures, protocol issues, and coverage gaps.
- Analyze simulation results and work closely with RTL Design, Architecture, and Validation teams.
Required Technical Skills:
- 6–10 years of hands-on experience in Design Verification.
- Strong programming/verification experience in SystemVerilog.
- Strong hands-on experience with UVM.
- Good understanding of Verilog/SystemVerilog simulation and debugging.
- Minimum 2+ years of experience with Ethernet and/or PCIe protocol verification.
- Good understanding of Ethernet MAC concepts and/or PCIe architecture/protocol.
- Experience with functional coverage, assertions, constrained-random verification, and regression testing.
If this opportunity interests you and your experience aligns with the above requirements, please share your updated resume along with the following details at your earliest convenience: