Job Role : Lead RTL Integration Engineer
Exp : 8+ years
Location : Bangalore
Requirements:
• Integrate 3rd-party IPs into the SoC and own the integration.
• Perform CDC (Clock Domain Crossing) analysis across multiple clock domains.
• Design/handle ASEP 8-port interfaces, including width conversion, async FIFO, routing, and SOP/EOP framing.
• Develop APB/SoC slave bus bridges and manage register maps/CSRs using RGGEN.
• Write SystemVerilog RTL and assertions and perform lint/CDC closure using Cadence/SpyGlass tools.
• Working knowledge of ASA-ML DLL, PCS, OAM, PTB, and ASEP layers; PHY datasheet/spec fluency
• Implement MBIST, LBIST, redundancy, and other safety mechanisms to meet Functional Safety (FuSa) requirements.