? We are Hiring: Senior DFT Engineer (6+ Years Experience) ?

Role: Senior DFT (Design for Test) Engineer

Experience: 6+ Years

Locations: Bangalore | Hyderabad | Chennai

Notice Period: Immediate to 15 Days (Mandatory)
Key Responsibilities:
• Lead and execute end-to-end DFT flow across complex SoC/ASIC designs.
• Implement Scan Insertion, ATPG (Stuck-at, At-speed/Transition), MBIST, and Boundary Scan (IJTAG / IEEE 1149.1 / 1500 / 1687).
• Conduct Gate-Level Simulations (GLS) with SDF back-annotation and resolve timing/simulation failures.
• Work closely with physical design, synthesis, and STA teams to ensure clean DFT timing closure and coverage target achievement.
• Support post-silicon bring-up, ATE pattern generation, and debug on silicon.

Key Qualifications:
• Experience:



6+ years of hands-on expertise in core DFT methodology and implementation.
• Tools: Proficiency in industry-standard DFT tools (Siemens Tessent, Synopsys DFTMAX/TetraMAX, or Cadence Modus).
• Technical Domain: Scan Compression, MBIST, ATPG, BSDL, IJTAG, and Silicon Debug.
• Notice Period: Immediate joiners or candidates with up to 15 days notice period.

How to Apply:

If you are looking for an exciting prospect or know someone who fits this role, please send your updated resume to [email protected] or send a direct message.
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📌 Senior DFT Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru