- 8 to 10+ Years of experience in DFT architecture, scan Insertion, and compression at the core level and SoC level.
- Experience in ATPG pattern generation and coverage analysis
- Experience with timing and no-timing simulations
- Experience in Memory-BIST
- Have an understanding of SSN architecture, clock architecture, and OCC
📌 DFT Lead Engineer (Hyderabad)
🏢 BITSILICA
📍 Hyderabad
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