- Own complete RTL-to-GDSII flow: floorplan, place, CTS, route, signoff
- Drive PPA optimization, timing, SI, IR/EM closure
- Lead and mentor a team of PD engineers; manage schedules and deliverables
- Interface with RTL, DFT, STA, Verification, Foundry, and Signoff teams
- Handle ECOs, tapeout readiness, and design reviews
- Improve PD methodologies, flows, and automation
- Solid hands-on PD expertise with Innovus / ICC2 / FusionCompiler / Tempus / PrimeTime /Etc.
- Experience in 28nm to 3nm nodes
- Solid scripting skills (TCL, Python/Perl/Shell)
- Proven ownership of block or full-chip tapeouts
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📌 Physical Design Lead (RTL-GDSII) (India)
🏢 Mirafra
📍 India