- Strong hands-on experience in RTL Design.
- Good understanding of Microarchitecture and design specifications.
- Experience in RTL integration and implementation.
- Hands-on involvement in design-related activities beyond QC/validation.
- Strong Verilog/SystemVerilog skills.
- Experience with ASIC/SoC/IP design flows.
- Positive debugging and problem-solving skills.
- Ability to work closely with Architecture, Verification and Physical Design teams.
Looking for engineers with strong core design ownership and hands-on implementation experience.