We are looking for a Senior Physical Design Engineer with solid hands-on expertise in EM/IR analysis and physical design sign-off for complex ASIC/SoC designs.
Key Responsibilities
- Perform EM/IR analysis, debugging and sign-off for block and full-chip designs.
- Analyze static/dynamic IR drop, electromigration and power integrity issues.
- Drive EM/IR closure through power-grid optimization, PG strengthening and physical ECOs.
- Work closely with Physical Design, STA, RTL, DFT and Power teams to resolve power integrity issues.
- Perform vector-based and vectorless EM/IR analysis and correlate results with design activity.
- Debug IR drop hotspots, EM violations and power-grid reliability issues.
- Support power planning, PG mesh/stripe optimization and power integrity sign-off.
- Analyze the impact of placement,
routing, clocking and power distribution on EM/IR.
- Automate analysis and reporting using Tcl/Python/Perl.
- Support tape-out and sign-off closure for advanced-node designs.
Required Skills
- 5–10 years of ASIC/SoC Physical Design experience.
- Strong hands-on experience in EM/IR analysis and closure.
- Experience with Cadence Voltus, Ansys RedHawk or equivalent.
- Good understanding of power distribution networks, IR drop, electromigration and power integrity.
- Strong knowledge of physical design, P&R; and sign-off flows.
- Understanding of STA, MMMC and advanced-node design challenges.
- Strong debugging and scripting skills.
- Experience with full-chip/block-level EM/IR sign-off preferred.